Technology scaling unfavorably affects the electrostatic discharge (ESD) protection of integrated circuits mainly by reducing MOSFET oxide and junction breakdown voltage, diode current shunting capability, and by increasing interconnect resistivity. The input/output (I/O) data-rate increasingly limits the capacitive budget, exacerbating the shrinkage of ESD design space.
Semiconductor-on-insulator (SOI) technology presents some distinctive challenges to ESD design. The buried oxide (BOX) layer makes vertical and deep body ESD structures infeasible. The lateral SOI diode based (“rail-based”) protection approach is becoming less effective in the high-current Charged Device Model (CDM) domain, owing to excessive voltage build-up along the ESD path involving power buses, power-clamps (Pclamp), and diodes. While various types of ESD devices have been proposed, there is a need for a suitable technique for ESD protection in fully depleted SOI (FDSOI) and/or partially depleted SOI (PDSOI) technology.
Accordingly, it is desirable to provide integrated circuits with lateral bipolar transistors on SOI structures. Also, it is desirable to provide integrated circuits with lateral bipolar transistors on SOI structures that provide electrostatic discharge protection. Further, it is desirable to provide methods for fabricating integrated circuits with lateral bipolar transistors on SOI structures. It is desirable to provide methods for fabricating lateral bipolar transistors on SOI structures that do not need any special or additional layers or masks and allow for integration into existing fabrication process flows. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.